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A 0.13μm CMOS Current Steering D/A Converter for PLC and VDSL Applications

AutorRuiz Amaya, Jesús; Fernández-Bootello, Juan Francisco; Rosa, José M. de la ; Delgado-Restituto, Manuel
Palabras claveCurrent Steering
Digital-to-Analog Converters
Fecha de publicaciónnov-2005
CitaciónJ. Ruiz-Amaya, J.F. Fernández-Bootello, J.M. de la Rosa and M. Delgado-Restituto: "A 12-bit 80MS/s Current Steering DAC for CMOS PLC/VDSL Applications", Proceeding of the 2005 Conference on Design of Circuits and Integrated Systems, Lisbon, November 2005.
ResumenThis paper describes the design of a 12-bit 80MS/s Digital-to-Analog converter implemented in a 0.13μm CMOS logic technology. The design has been computer-aided by a developed toolbox for the simulation and verification of Nyquist-Rate Analog-to-Digital and Digital-to-Analog converters in MATLAB. The converter is segmented in an unary current-cell matrix for 8 MSB's and a binary-weighted array for 4 LSB's. Current sources of the converter are laid out separately from current-cell switching matrix core block and distributed in double centroid to reduce random errors and transient noise coupling. The linearity errors caused by remaining gradient errors are reduced by a modified Q2 Random-Walk switching sequence. Transistor-level simulation results show that the Spurious-Free Dynamic-Range is better than 58.5dB up to 80MS/s. The estimated Signal-to-Noise Distortion Ratio yield is 99.7% and better than 58dB from DC to Nyquist frequency. Multi-Tone Power Ratio is higher than 59dB for several DMT test signals. The converter dissipates less than 129mW from a 3.3V supply and occupies less than 1.7mm2 active area.
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